The invention relates to a process for the production of a single transistor memory cell, in which in a semiconductor crystal of one conduction type, not only two zones of the opposite conduction type which are separated by a strip of the former type, but also a recess in the region of these two zones which is limited with plane surfaces converging toward the bottom are produced in such a way that the two zones within the recess reach the semiconductor surface. Also, the pn junctions of the two zones at the part of the semiconductor crystal having the original conduction type are configured differently so that the capacity of the memory cell to be produced is at least predominantly represented by only one of the two pn junctions. Finally, an insulating layer is provided within the recess and a gate electrode is provided thereon capacitively controlling the two pn junctions.
As is known, a process of this kind leads to a so-called V-MOS transistor, such as is described, for example, in the publication "Electronics" (Apr. 1, 1976), Pages 77 and 78 and incorporated herein by reference. In order to produce the transistor, the starting point is an n.sup.+ -doped disk-shaped silicon monocrystal on whose surface a p-doped monocrystalline silicon layer is epitaxially deposited. The surface of the epitaxial layer is then provided with a diffusion mask with the aid of which an n.sup.+ conductive zone is then produced by diffusion. This forms the drain zone; the substrate forms the source zone, and the non-re-doped intermediate layer between the two zones forms the channel-forming zone of the field effect transistor of the memory cell. For completion, a recess with a V-shaped longitudinal profile is produced in the region of the drain zone using an etching mask. The lowest point of the profile extends into the n+ doped substrate. The semiconductor surface in the recess is then covered with a thin oxide layer on which the gate electrode of the field effect transistor is then applied. The designation "V-MOS" results from the V-shaped recess.
In order to now develop a V-MOS transistor of this kind into a single transistor memory cell, one of the two zones of the opposite conduction type, for example, the source zone, is for example usually given a stronger doping than the other of these two zones, for example, the drain zone. In addition, this source zone is individually assigned to the individual memory cell in an integrated memory matrix constructed of such memory cells, while the drain zone is frequently also employed to serve as a bit line in connection to further memory cells arranged within the same matrix column as the cell in question. In order to produce an arrangement of this kind, the starting point is a p conductive substrate on whose surface an n+ doped source zone along the lines of a buried layer is produced on its surface. A p doped semiconductor layer is then epitaxially deposited on the substrate provided with the source zone or zones, respectively, and in this semiconductor layer the drain zones, the V-shaped recesses and the gate electrodes of the individual field effect transistors are produced.
Obviously an advantage of the V-MOS technique in supplying these memory cells lies in the fact that integrated semiconductor memories with especially high cell density can be produced. However, the usual production processes operate with epitaxial layers.